HD64F2168 Datasheet, PDF (536/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

4. SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t_cyc, as shown in section 25, Electrical
Characteristics. Note that the I²C bus interface AC timing specification will not be met with a
system clock frequency of less than 5 MHz.
5. The I²C bus interface specification for the SCL rise time t_sr is 1000 ns or less (300 ns for high-
speed mode). In master mode, the I²C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t_sr (the time for SCL to go from low to V_IH) exceeds
the time determined by the input clock of the I²C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 15.12.
Table 15.12 Permissible SCL Rise Time (t_sr) Values
TCSS IICXn
t_cyc
Indi-
cation
I²C Bus
Spe-
cifica-
tion φ = 5
(Max.) MHz
Time Indication [ns]
φ=8
MHz
φ = 10 φ = 16 φ = 20 φ = 25 φ = 33
MHz MHz MHz MHz MHz
0
0
1
7.5 t_cyc Standard 1000 1000 937
750
468
375
300
227
mode
High- 300 300 300 300 300 300 300 227
speed
mode
17.5 t_cyc Standard 1000 1000 1000 1000 1000 875
700
530
mode
1
0
High- 300
speed
mode
1
1
37.5 t_cyc Standard 1000
mode
High- 300
speed
mode
Note: n = 0 to 5
300
1000
300
300
1000
300
300
1000
300
300
1000
300
300
1000
300
300
1000
300
300
1000
300
6. The I²C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I²C bus interface SCL and SDA output timing is prescribed by t_cyc, as shown in
table 15.11. However, because of the rise and fall times, the I²C bus interface specifications
may not be satisfied at the maximum transfer rate. Table 15.13 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fall times.
Rev. 3.00, 03/04, page 496 of 830