HD64F2168 Datasheet, PDF (545/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14. Note on ACKE and TRS bits in slave mode
In the I²C bus interface, if 1 is received as the acknowledge bit value (ACKB = 1) in transmit
mode (TRS = 1) and then the address is received in slave mode without performing appropriate
processing, interrupt handling may start at the rising edge of the 9th clock pulse even when the
address does not match. Similarly, if the start condition and address are transmitted from the
master device in slave transmit mode (TRS = 1), the ICDRE flag is set, and 1 is received as the
acknowledge bit value (ACKB = 1), the IRIC flag may be set thus causing an interrupt source
even when the address does not match.
To use the I²C bus interface module in slave mode, be sure to follow the procedures below.
 When having received 1 as the acknowledge bit value for the last transmit data at the end
of a series of transmit operation, clear the ACKE bit in ICCR once to initialize the ACKB
bit to 0.
 Set receive mode (TRS = 0) before the next start condition is input in slave mode.
Complete transmit operation by the procedure shown in figure 15.23, in order to switch
from slave transmit mode to slave receive mode.
15. Notes on Arbitration Lost in Master Mode Operation
The I²C bus interface recognizes the data in transmit/receive frame as an address when
arbitration is lost in master mode and a transition to slave receive mode is automatically
carried out.
When arbitration is lost not in the first frame but in the second frame or subsequent frame,
transmit/receive data that is not an address is compared with the value set in the SAR or SARX
register as an address. If the receive data matches with the address in the SAR or SARX
register, the I²C bus interface erroneously recognizes that the address call has occurred. (See
figure 15.35.)
In multi-master mode, a bus conflict could happen. When the I²C bus interface is operated in
master mode, check the state of the AL bit in the ICSR register every time after one frame of
data has been transmitted or received.
When arbitration is lost during transmitting the second frame or subsequent frame, take
avoidance measures.
Rev. 3.00, 03/04, page 505 of 830