HD64F2168 Datasheet, PDF (19/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14.11.1 Features................................................................................................................ 428
14.11.2 Register Descriptions........................................................................................... 428
14.11.3 CRC Operation Circuit Operation........................................................................ 430
14.11.4 Note on CRC Operation Circuit........................................................................... 433
Section 15 I²C Bus Interface (IIC) .....................................................................435
15.1 Features............................................................................................................................. 435
15.2 Input/Output Pins .............................................................................................................. 438
15.3 Register Descriptions ........................................................................................................ 439
15.3.1 I²C Bus Data Register (ICDR) ............................................................................. 439
15.3.2 Slave Address Register (SAR)............................................................................. 440
15.3.3 Second Slave Address Register (SARX) ............................................................. 441
15.3.4 I²C Bus Mode Register (ICMR)........................................................................... 442
15.3.5 I²C Bus Transfer Rate Select Register (IICX3).................................................... 443
15.3.6 I²C Bus Control Register (ICCR)......................................................................... 446
15.3.7 I²C Bus Status Register (ICSR)............................................................................ 455
15.3.8 I²C Bus Extended Control Register (ICXR)......................................................... 459
15.3.9 I²C SMBus Control Register (ICSMBCR)........................................................... 463
15.4 Operation .......................................................................................................................... 465
15.4.1 I²C Bus Data Format ............................................................................................ 465
15.4.2 Initialization ......................................................................................................... 467
15.4.3 Master Transmit Operation .................................................................................. 467
15.4.4 Master Receive Operation.................................................................................... 471
15.4.5 Slave Receive Operation...................................................................................... 478
15.4.6 Slave Transmit Operation .................................................................................... 485
15.4.7 IRIC Setting Timing and SCL Control ................................................................ 488
15.4.8 Operation Using the DTC .................................................................................... 490
15.4.9 Noise Canceler..................................................................................................... 492
15.4.10 Initialization of Internal State .............................................................................. 492
15.5 Interrupt Source ................................................................................................................ 494
15.6 Usage Notes ...................................................................................................................... 495
Section 16 LPC Interface (LPC) ........................................................................507
16.1 Features............................................................................................................................. 507
16.2 Input/Output Pins .............................................................................................................. 509
16.3 Register Descriptions ........................................................................................................ 510
16.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1)................................. 512
16.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)................................. 518
16.3.3 Host Interface Control Register 4 (HICR4) ......................................................... 521
16.3.4 LPC Channel 3 Address Register H, L (LADR3H, LADR3L)............................ 522
16.3.5 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L).................... 526
16.3.6 Input Data Registers 1 to 3 (IDR1 to IDR3) ........................................................ 527
16.3.7 Output Data Registers 0 to 3 (ODR1 to ODR3) .................................................. 527
Rev. 3.00, 03/04, page xix of xl