HD64F2168 Datasheet, PDF (481/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

15.3.3 Second Slave Address Register (SARX)
SARX sets the second slave address and selects the communication format. In slave mode,
transmit/receive operations by the DTC are possible when the received address matches the
second slave address. When the LSI is in slave mode with the I²C bus format selected, if the FSX
bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after
a start condition, the LSI operates as the slave device specified by the master device. SARX can be
accessed only when the ICE bit in ICCR is cleared to 0.
Initial
Bit Bit Name Value
7
SVAX6 All 0
6
SVAX5
5
SVAX4
4
SVAX3
3
SVAX2
2
SVAX1
1
SVAX0
0
FSX
1
R/W Description
R/W Second Slave Address
Set the second slave address.
R/W Format Select X
Selects the communication format together with the FS bit
in SAR. Refer to table 15.2.
Table 15.2 Transfer Format
SAR
FS
0
1
SARX
FSX
0
1
0
1
Operating Mode
I²C bus format
• SAR and SARX slave addresses recognized
• General call address recognized
I²C bus format
• SAR slave address recognized
• SARX slave address ignored
• General call address recognized
I²C bus format
• SAR slave address ignored
• SARX slave address recognized
• General call address ignored
Clocked synchronous serial format
• SAR and SARX slave addresses ignored
• General call address ignored
Rev. 3.00, 03/04, page 441 of 830