HD64F2168 Datasheet, PDF (142/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

• Multiplex bus interface
No Wait Inserted
Wait Inserted
Address
Data
Address
Data
256-kbyte
extended area
2 states *
2 states
2 states *
(3 + wait) states
CP extended area 2 states *
2 states
2 states *
(3 + wait) states
IOS extended area 2 states *
2 states
2 states *
(3 + wait) states
Note: * A wait cycle is inserted by the setting of the WC22 bit.
• Basic bus interface
2-state access or 3-state access can be selected for each area.
Program wait states can be inserted for each area.
• Burst ROM interface
In normal extended mode
A burst ROM interface can be set for basic extended areas.
1-state access or 2-state access can be selected for burst access.
• Idle cycle insertion
In normal extended mode
An idle cycle can be inserted for external write cycles immediately after external read cycles.
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC.
Rev. 3.00, 03/04, page 102 of 830