HD64F2168 Datasheet, PDF (829/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 25.5 External Clock Input Conditions
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item
Symbol Min.
External clock input low level t
10
EXL
pulse width
External clock input high level t_EXH
10
pulse width
External clock input rising time t_EXr

External clock input falling time t_EXf

Clock low level pulse width t_CL
0.4
Clock high level pulse width t
0.4
CH
External clock output
stabilization delay time
t_DEXT*
500
Note: * t_DEXT includes a RES pulse width (t_RESW).
Max.


5
5
0.6
0.6

Unit
ns
ns
ns
ns
t_cyc
t
cyc
µs
Test
Conditions
Figure 25.7
Figure 25.4
Figure 25.8
Table 25.6 Subclock Input Conditions
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ SUB = 32.768 kHz, 5 MHz to 33 MHz
Item
Symbol Min.
Subclock input low level pulse t
EXCLL

width
Subclock input high level pulse t_EXCLH

width
Subclock input rising time
t_EXCLr

Subclock input falling time
t_EXCLf

Clock low level pulse width t
0.4
CL
Clock high level pulse width t
0.4
CH
Typ.
15.26
Max.

15.26 

10

10

0.6

0.6
Unit
µs
µs
ns
ns
t
cyc
t
cyc
Measureme
nt Condition
Figure 25.9
Figure 25.4
t_cyc
t_CH
t_Cf
φ
t_CL
t_Cr
Figure 25.4 System Clock Timing
Rev. 3.00, 03/04, page 789 of 830