HD64F2168 Datasheet, PDF (313/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

1 conversion cycle
t_f1
t_f2
t_f255
t_f256
t_H1
t_H2
t_H3
t_H255
t_f1 = t_f2 = t_f3 = ··· = t_f255 = t_f256 = T× 64
t_H1 + t_H2 + t_H3 + ··· + t_H255 + t_H256 = T_H
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
t_f1
t_f2
t_f63
t_H256
t_f64
t_H1
t_H2
t_H3
t_f1 = t_f2 = t_f3 = ··· = t_f63 = t_f64 = T× 256
t_H1 + t_H2 + t_H3 + ··· + t_H63 + t_H64 = T_H
t_H63
t_H64
b. CFS = 1 [base cycle = resolution (T) × 256]
Figure 10.4 Output Waveform (OS = 1, DADR corresponds to T_H)
An example of the additional pulses when CFS = 1 (base cycle = resolution (T) × 256) and OS = 1
(inverted PWM output) is described below. When CFS = 1, the upper eight bits (DA13 to DA6) in
DADR determine the duty cycle of the base pulse while the subsequent six bits (DA5 to DA0)
determine the locations of the additional pulses as shown in figure 10.5.
Table 10.4 lists the locations of the additional pulses.
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS
Duty cycle of base pulse
Location of additional pulses
1
1
Figure 10.5 D/A Data Register Configuration when CFS = 1
In this example, DADR = H'0207 (B'0000 0010 0000 0111). The output waveform is shown in
figure 10.6. Since CFS = 1 and the value of the upper eight bits is B'0000 0010, the high width of
the base pulse duty cycle is 2/256 × (T).
Since the value of the subsequent six bits is B'0000 01, an additional pulse is output only at the
location of base pulse No. 63 according to table 10.4. Thus, an additional pulse of 1/256 × (T) is to
be added to the base pulse.
Rev. 3.00, 03/04, page 273 of 830