HD64F2168 Datasheet, PDF (365/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

12.5.5 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
12.9 shows the timing of clearing the counter by an external reset input.
φ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 12.9 Timing of Counter Clear by External Reset Input
12.5.6 Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure
12.10 shows the timing of OVF flag setting.
φ
TCNT
Overflow signal
H'FF
H'00
OVF
Figure 12.10 Timing of OVF Flag Setting
Rev. 3.00, 03/04, page 325 of 830