HD64F2168 Datasheet, PDF (614/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.4.5 A20 Gate
The A20 gate signal can mask address A20 to emulate an addressing mode used by personal
computers with an 8086-family CPU*. A regular-speed A20 gate signal can be output under
firmware control. The fast A20 gate function that is speeded up by the hardware is enabled by
setting the FGA20E bit to 1 in HICR0.
Note: * An Intel microcomputer
Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1
command followed by data. When the slave processor (this LSI) receives data, it normally uses an
interrupt routine activated by the IBFI1 interrupt to read IDR1. If the data follows an H'D1
command, firmware copies bit 1 of the data and outputs it at the gate A20 pin.
Fast A20 Gate Operation: The internal state of GA20 output is initialized to 1 when FGA20E =
0. When the FGA20E bit is set to 1, PD3/GA20 is used for output of a fast A20 gate signal. The
state of the PD3/GA20 pin can be monitored by reading the GA20 bit in HICR2.
The initial output from this pin will be a logic 1, which is the initial value. Afterward, the host
processor can manipulate the output from this pin by sending commands and data. This function is
only available via the IDR1 register. The LPC interface decodes commands input from the host.
When an H'D1 host command is detected, bit 1 of the data following the host command is output
from the GA20 output pin. This operation does not depend on firmware or interrupts, and is faster
than the regular processing using interrupts. Table 16.6 shows the conditions that set and clear
GA20 (PD3). Figure 16.8 shows the GA20 output in flowchart form. Table 16.7 indicates the
GA20 output signal values.
Table 16.6 GA20 (PD3) Set/Clear Conditions
Pin Name
GA20 (PD3)
Setting Condition
When bit 1 of the data that follows an
H'D1 host command is 1
Clearing Condition
When bit 1 of the data follows an H'D1
host command is 0
Rev. 3.00, 03/04, page 574 of 830