HD64F2168 Datasheet, PDF (309/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

10.5 Operation
A PWM waveform like the one shown in figure 10.2 is output from the PWX pin. DA13 to DA0
in DADR corresponds to the total width (T_L) of the low (0) pulses output in one conversion cycle
(256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 0, this waveform is directly
output. When OS = 1, the output waveform is inverted, and DA13 to DA0 in DADR value
corresponds to the total width (T_H) of the high (1) output pulses. Figures 10.3 and 10.4 show the
types of waveform output available.
t_f
Base cycle
(T × 64 or T × 256)
1 conversion cycle
(T × 2¹⁴ (= 16384))
t_L
T: Resolution
m
T_L = Σ t_Ln (OS = 0)
n=1
(When CFS = 0, m = 256
When CFS = 1, m = 64)
Figure 10.2 PWMX (D/A) Operation
Table 10.3 summarizes the relationships between the CKS and CFS bit settings and the resolution,
base cycle, and conversion cycle. The PWM output remains fixed unless DA13 to DA0 in DADR
contain at least a certain minimum value. The relationship between the OS bit and the output
waveform is shown in figures 10.3 and 10.4.
Rev. 3.00, 03/04, page 269 of 830