HD64F2168 Datasheet, PDF (706/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

20.5.2 Software Protection
Software protection is set up in any of two ways: by disabling the downloading of on-chip
programs for programming and erasing and by means of a key code.
Table 20.10 Software Protection
Item
Protection by the
SCO bit
Protection by the
FKEY register
Function to be Protected
Description
Download Program/Erase
• The program/erase-protected state is
entered by clearing the SCO bit in
FCCS which disables the downloading
of the programming/erasing programs.
• Downloading and
programming/erasing are disabled
unless the required key code is written
in FKEY. Different key codes are used
for downloading and for
programming/erasing.
20.5.3 Error Protection
Error protection is a mechanism for aborting programming or erasure when an error occurs, in the
form of the microcomputer entering runaway during programming/erasing of the flash memory or
operations that are not according to the established procedures for programming/erasing. Aborting
programming or erasure in such cases prevents damage to the flash memory due to excessive
programming or erasing.
If the microcomputer malfunctions during programming/erasing of the flash memory, the FLER
bit in the FCCS register is set to 1 and the error-protection state is entered, and this aborts the
programming or erasure.
The FLER bit is set in the following conditions:
1. When an interrupt such as NMI occurs during programming/erasing.
2. When the flash memory is read during programming/erasing (including a vector read or an
instruction fetch).
3. When a SLEEP instruction (including software-standby mode) is executed during
programming/erasing.
4. When a bus master other than the CPU, such as the DTC, gets bus mastership during
programming/erasing.
Rev. 3.00, 03/04, page 666 of 830