HD64F2168 Datasheet, PDF (31/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Figure 15.29 Notes on Reading Master Receive Data ................................................................ 500
Figure 15.30 Flowchart for Start Condition Issuance Instruction for Retransmission
and Timing............................................................................................................. 501
Figure 15.31 Stop Condition Issuance Timing ........................................................................... 502
Figure 15.32 IRIC Flag Clearing Timing When WAIT = 1 ....................................................... 502
Figure 15.33 ICDR Register Read and ICCR Register Access Timing in Slave Transmit
Mode ...................................................................................................................... 503
Figure 15.34 TRS Bit Set Timing in Slave Mode....................................................................... 504
Figure 15.35 Diagram of Erroneous Operation when Arbitration Lost ...................................... 506
Section 16 LPC Interface (LPC)
Figure 16.1 Block Diagram of LPC............................................................................................ 508
Figure 16.2 Typical LFRAME Timing....................................................................................... 569
Figure 16.3 Abort Mechanism .................................................................................................... 569
Figure 16.4 SMIC Write Transfer Flow ..................................................................................... 570
Figure 16.5 SMIC Read Transfer Flow ...................................................................................... 571
Figure 16.6 BT Write Transfer Flow .......................................................................................... 572
Figure 16.7 BT Read Transfer Flow........................................................................................... 573
Figure 16.8 GA20 Output ........................................................................................................... 575
Figure 16.9 Power-Down State Termination Timing ................................................................. 580
Figure 16.10 SERIRQ Timing .................................................................................................... 581
Figure 16.11 Clock Start or Speed-Up........................................................................................ 583
Figure 16.12 HIRQ Flowchart (Example of Channel 1)............................................................. 586
Section 17 D/A Converter
Figure 17.1 Block Diagram of D/A Converter ........................................................................... 589
Figure 17.2 D/A Converter Operation Example ......................................................................... 593
Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ........................................................................... 596
Figure 18.2 A/D Conversion Timing .......................................................................................... 602
Figure 18.3 External Trigger Input Timing ................................................................................ 603
Figure 18.4 A/D Conversion Accuracy Definitions.................................................................... 605
Figure 18.5 A/D Conversion Accuracy Definitions.................................................................... 605
Figure 18.6 Example of Analog Input Circuit ............................................................................ 606
Figure 18.7 Example of Analog Input Protection Circuit ........................................................... 608
Figure 18.8 Analog Input Pin Equivalent Circuit ....................................................................... 608
Section 20 Flash Memory (0.18-µm F-ZTAT Version)
Figure 20.1 Block Diagram of Flash Memory............................................................................ 612
Figure 20.2 Mode Transition of Flash Memory.......................................................................... 613
Figure 20.3 Flash Memory Configuration .................................................................................. 615
Figure 20.4 Block Division of User MAT .................................................................................. 617
Figure 20.5 Overview of User Procedure Program..................................................................... 618
Figure 20.6 System Configuration in Boot Mode....................................................................... 639
Rev. 3.00, 03/04, page xxxi of xl