HD64F2168 Datasheet, PDF (90/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

End of bus request
Bus request
End of bus
request
Bus-released state
End of
exception
handling
Program execution
state
Bus
request
Request for
exception
handling
SLEEP
instruction
with
LSON = 0,
PSS = 0,
SSBY = 1
SLEEP
instruction
with
LSON = 0,
SSBY = 0
Sleep mode
Exception-handling state
RES = high
Interrupt
request
External interrupt
request
Software standby mode
Reset state^*1
STBY = high, RES = low
Hardware standby mode^*2
Power-down state^*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
2. From any state, a transition to hardware standby mode occurs when STBY goes low.
3. The power-down state also includes watch mode, subactive mode, subsleep mode, etc. For details,
refer to section 23, Power-Down Modes.
Figure 2.13 State Transitions
Rev. 3.00, 03/04, page 50 of 830