HD64F2168 Datasheet, PDF (359/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Bit
Bit Name Initial Value R/W Description
1
OS1
0
0
OS0
0
R/W Output Select 1 and 0
R/W _{These bits specify how the TMOX pin output level is}
to be changed by compare-match A of TCORA_X
and TCNT_X.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
Note: * Only 0 can be written, for flag clearing.
12.3.6 Input Capture Register (TICR)
TICR is an 8-bit register. The contents of TCNT are transferred to TICR at the rising edge of the
external reset input. TICR cannot be directly accessed by the CPU.
12.3.7 Time Constant Register C (TCORC)
TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always
compared with TCNT. When a match is detected, a compare-match C signal is generated.
However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of
TICR is disabled. TCORC is initialized to H'FF.
12.3.8 Input Capture Registers R and F (TICRR and TICRF)
TICRR and TICRF are 8-bit read-only registers. While the ICST bit in TCONRI is set to 1, the
contents of TCNT are transferred at the rising edge and falling edge of the external reset input in
that order. The ICST bit is cleared to 0 when one capture operation ends. TICRR and TICRF are
initialized to H'00.
TICRR and TICRF can be accessed when the KINWUE bit in SYSCR is 0 and the TMRX/Y bit in
TCONRS is 0. See section 3.2.2, System Control Register (SYSCR).
Rev. 3.00, 03/04, page 319 of 830