HD64F2168 Datasheet, PDF (840/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

25.3.4 Multiplex Bus Timing
Table 25.9 shows the Multiplex bus interface timing. In subclock (φSUB = 32.768 kHz) operation,
external expansion mode operation cannot be guaranteed.
Table 25.9 Multiplex Bus Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item
Symbol
Address delay time
t
AD
Address setup time 2 t
AS2
Address hold time 2
t
AH2
CS delay time (IOS,
t_CSD
CS256, CPCS1)
AH delay time
t_AHD
RD delay time 1
t_RSD1
RD delay time 2
t_RSD2
Read data setup time t
RDS
Read data hold time
t
RDH
Read data access time 2 t
ACC2
Read data access time 4 t
ACC4
Read data access time 6 t_ACC6
Read data access time 7
WR delay time 1
WR delay time 2
WR pulse width time 1
WR pulse width time 2
t_ACC7
t_WRD1
t_WRD2
t_WSW1
t
WSW2
Write data delay time t
WDD
Write data setup time t
WDS
Write data hold time
t
WDH
Min..
—
0.5
×
t
cyc
−
15
1.0
×
t
cyc
−
10
—
Max.
15
—
—
15
Unit Test Conditions
ns Figures 25.17,
25.18
—
—
—
15
0
—
—
—
—
—
—
1.0 × t_cyc − 20
1.5
×
t
cyc
−
20
—
0
0.5
×
t
cyc
−
5
15
15
15
—
—
1.5
×
t
cyc
−
25
2.5
×
t
cyc
−
25
3.5 × t_cyc − 25
4.5 × t_cyc − 25
15
15
—
—
25
—
—
Rev. 3.00, 03/04, page 800 of 830