HD64F2168 Datasheet, PDF (463/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14.10.6 Restrictions on Using DTC
When the external clock source is used as a synchronization clock, update TDR by the DTC and
wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit
clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure
14.38).
When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC
activation source.
SCK
TDRE
Serial data
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7
Note: When external clock is supplied, t must be more than four clock cycles.
Figure 14.38 Sample Transmission using DTC in Clock Synchronous Mode
14.10.7 SCI Operations during Mode Transitions
Transmission: Before making the transition to module stop, software standby, or sub-sleep mode,
stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of
the output pins during each mode depend on the port settings, and the pins output a high-level
signal after mode cancellation. If the transition is made during data transmission, the data being
transmitted will be undefined.
To transmit data in the same transmission mode after mode cancellation, set TE to 1, read SSR,
write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different
transmission mode, initialize the SCI first.
Figure 14.39 shows a sample flowchart for mode transition during transmission. Figures 14.40 and
14.41 show the pin states during transmission.
Before making the transition from the transmission mode using DTC transfer to module stop,
software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). Setting
TE and TIE to 1 after mode cancellation generates a TXI interrupt request to start transmission
using the DTC.
Rev. 3.00, 03/04, page 423 of 830