HD64F2168 Datasheet, PDF (625/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

set to 1. In order to clear a host interrupt request, it is necessary to clear the host interrupt enable
bit.
Table 16.12 summarizes the methods of setting and clearing these bits, and figure 16.12 shows the
processing flowchart.
Table 16.12 HIRQ Setting and Clearing Conditions
Host Interrupt Setting Condition
Clearing Condition
HIRQ1
Slave writes to ODR1, then reads 0 from Slave writes 0 to bit IRQ1E1, or host
bit IRQ1E1, and writes 1
reads ODR1
HIRQ12
Slave writes to ODR1, then reads 0 from Slave writes 0 to bit IRQ12E1, or host
bit IRQ12E1, and writes 1
reads ODR1
SMI
(IEDIR = 0)
Slave
Slave
• writes to ODR2, then reads 0 from bit • writes 0 to bit SMIE2, or host
SMIE2, and writes 1
reads ODR2
SMI
(IEDIR3 = 0)
Slave
Slave
• writes to ODR3, then reads 0 from bit • writes 0 to bit SMIE3A, or host
SMIE3A, and writes 1
reads ODR3
• writes to TWR15, then reads 0 from • writes 0 to bit SMIE3B, or host
bit SMIE3B, and writes 1
reads TWR15
SMI
(IEDIR = 1)
Slave
• reads 0 from bit SMIE2, then writes 1 • Slave writes 0 to bit SMIE2
SMI
(IEDIR3 = 1)
Slave
• reads 0 from bit SMIE3A, then writes
1
• reads 0 from bit SMIE3B, then writes
1
Slave
• writes 0 to bit SMIE3A
• writes 0 to bit SMIE3B
HIRQi
Slave
Slave
(i = 6, 9, 10, 11) _{• writes to ODR2, then reads 0 from bit • writes 0 to bit IRQiE2, or host}
(IEDIR = 0)
IRQiE2, and writes 1
reads ODR2
HIRQi
Slave
Slave
(i = 6, 9, 10, 11) _{• writes to ODR3, then reads 0 from bit • writes 0 to bit IRQiE3, or host}
(IEDIR3 = 0)
IRQiE3 and writes 1
reads ODR3
HIRQi
Slave
Slave
(i = 6, 9, 10, 11) _{• reads 0 from bit IRQiE2, then writes 1 • writes 0 to bit IRQiE2}
(IEDIR = 1)
HIRQi
Slave
Slave
(i = 6, 9, 10, 11) _{• reads 0 from bit IRQiE3, then writes 1 • writes 0 to bit IRQiE3}
(IEDIR3 = 1)
Rev. 3.00, 03/04, page 585 of 830