HD64F2168 Datasheet, PDF (540/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

SDA
Bit 0
A
SCL
8
9
Internal clock
BBSY bit
Master receive mode
Stop condition
(a)
ICDR read
disabled period
Start condition
Execution of instruction
for issuing stop condition
(write 0 to BBSY and SCP)
Confirmation of stop
condition issuance
(read BBSY = 0)
Start condition
issuance
Figure 15.29 Notes on Reading Master Receive Data
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in
ICXR.
8. Notes on start condition issuance for retransmission
Figure 15.30 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. Write the
transmit data to ICDR after the start condition for retransmission is issued and then the start
condition is actually generated.
Rev. 3.00, 03/04, page 500 of 830