HD64F2168 Datasheet, PDF (452/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransfer frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(n + 1) th
transfer frame
Ds D0 D1 D2 D3 D4
TDRE
TEND
FER/ERS
Transfer from TDR to TSR
Transfer from TDR to TSR
[2]
Transfer from TDR to TSR
[3]
[1]
[3]
Figure 14.29 Data Re-transfer Operation in SCI Transmission Mode
Note that the TEND flag is set in different timings depending on the GM bit setting in SMR,
which is shown in figure 14.30.
I/O data
TXI
(TEND interrupt)
GM = 0
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Guard time
12.5 etu
GM = 1
11.0 etu
[Legend]
Ds:
Start bit
D0 to D7:Data bits
Dp:
Parity bit
DE:
Error signal
etu:
Element Time Unit (time taken to transfer one bit)
Figure 14.30 TEND Flag Set Timings during Transmission
Rev. 3.00, 03/04, page 412 of 830