HD64F2168 Datasheet, PDF (392/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Asynchronous Mode:
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
• Average transfer rate generator (SCI_0 and SCI_2): 460.606 kbps or 115.152 kbps selectable
at 10.667-MHz operation; 720 kbps, 460.784 kbps, 230.392 kbps, or 115.196 kbps selectable
at 16- or 24-MHz operation; 230.392 kbps or 115.196 kbps selectable at 20-MHz operation;
and 720 kbps selectable at 32-MHz operation
Clock Synchronous Mode:
• Data length: 8 bits
• Receive error detection: Overrun errors
• SCI channel selectable (SCI_0 and SCI_2): When SSE0I = 1, TxD0 = high-impedance state
and SCK0 = fixed to high input; when SSE2I = 1, TxD2 = high-impedance state and SCK2 =
fixed to high input
Smart Card Interface:
• An error signal can be automatically transmitted on detection of a parity error during reception
• Data can be automatically re-transmitted on detection of a error signal during transmission
• Both direct convention and inverse convention are supported
Figure 14.1 shows a block diagram of SCI_1, and figure 14.2 shows a block diagram of SCI_0 and
SCI_2.
Rev. 3.00, 03/04, page 352 of 830