HD64F2168 Datasheet, PDF (405/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Bit Bit Name Initial Value R/W Description
5
ORER
0
R/(W)* Overrun Error
[Setting condition]
When the next serial reception is completed while
RDRF = 1
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
4
FER
0
R/(W)* Framing Error
[Setting condition]
When the stop bit is 0
[Clearing condition]
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is checked.
3
PER
0
R/(W)* Parity Error
[Setting condition]
When a parity error is detected during reception
[Clearing condition]
When 0 is written to PER after reading PER = 1
2
TEND
1
R
Transmit End
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE =
1
• When a TXI interrupt request is issued allowing
DTC to write data to TDR
1
MPB
0
R
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
frame. When the RE bit in SCR is cleared to 0 its
previous state is retained.
0
MPBT
0
R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to
the transmit frame.
Note: * Only 0 can be written, to clear the flag.
Rev. 3.00, 03/04, page 365 of 830