HD64F2168 Datasheet, PDF (609/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

The timing of the LFRAME, LCLK, and LAD signals is shown in figures 16.2 and 16.3.
LCLK
LFRAME
LAD3 to LAD0
Start
ADDR TAR Sync Data TAR Start
Cycle type,
direction,
and size
Number of clocks ¹
1
4
2
1
2
2
1
Figure 16.2 Typical LFRAME Timing
LCLK
LFRAME
LAD3 to LAD0
Start
ADDR
Cycle type,
direction,
and size
TAR Sync
Slave must stop driving
Too many Syncs
cause timeout
Master will
drive high
Figure 16.3 Abort Mechanism
16.4.3 SMIC Mode Transfer Flow
Figure 16.4 shows the write transfer flow and figure 16.5 shows the read transfer flow in SMIC
mode.
Rev. 3.00, 03/04, page 569 of 830