HD64F2168 Datasheet, PDF (517/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

[13] Read the IRTR flag in ICSR.
If the IRTR flag is 0, execute step [14] to clear the IRIC flag to 0 to release the wait state.
If the IRTR flag is 1 and data reception is complete, execute step [15] to issue the stop
condition.
[14] If IRTR flag is 0, clear the IRIC flag to 0 to release the wait state.
Execute step [12] to read the IRIC flag to detect the end of reception.
[15] Clear the WAIT bit in ICMR to cancel the wait mode.
Clearing of the IRIC flag should be done while WAIT = 0. (If the WAIT bit is cleared to 0
after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the
stop condition may not be issued correctly.)
[16] Read the last ICDR receive data.
[17] Clear the BBSY bit and SCP bit to 0 in ICCR. This changes SDA from low to high when
SCL is high, and generates the stop condition.
Master transmit mode Master receive mode
SCL
(master output) 9
SDA
A
(slave output)
SDA
(master output)
IRIC
IRTR
ICDR
1 23 4 56 78
9 1 23 4 5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Data 1
[3]
[3]
A
Data 2
[4]IRTR=0
[4] IRTR=1
Data 1
User processing [1] TRS cleared to 0 [2] ICDR read
IRIC clear to 0
(dummy read)
[6] IRIC clear
(to end wait insertion)
[5]
ICDR read
(Data 1)
[6] IRIC clear
Figure 15.15 Master Receive Mode Operation Timing Example
(MLS = ACKB = 0, WAIT = 1)
Rev. 3.00, 03/04, page 477 of 830