HD64F2168 Datasheet, PDF (679/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

The system configuration diagram in boot mode is shown in figure 20.6. For details on the pin
setting in boot mode, see table 20.5. The NMI and other interrupts are ignored in boot mode.
However, the NMI and other interrupts should be disabled in the user system.
This LSI
Host
Boot
programming ^{Control command, program data}
tool and program
data
Reply response
Control command,
analysis execution
software (on-chip)
RxD1
On-chip SCI_1
TxD1
Flash
memory
On-chip RAM
Figure 20.6 System Configuration in Boot Mode
(1) SCI Interface Setting by Host
When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communica-
tion data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format
is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the
host by means of the measured low period and transmits the bit adjustment end sign (1 byte of
H'00) to the host. The host must confirm that this bit adjustment end sign (H'00) has been received
normally and transmits 1 byte of H'55 to this LSI. When reception is not executed normally, boot
mode is initiated again (reset) and the operation described above must be executed. The bit rate
between the host and this LSI is not matched by the bit rate of transmission by the host and system
clock frequency of this LSI. To operate the SCI normally, the transfer bit rate of the host must be
set to 4,800 bps, 9,600 bps, or 19,200 bps.
The system clock frequency, which can automatically adjust the transfer bit rate of the host and
the bit rate of this LSI, is shown in table 20.6. Boot mode must be initiated in the range of this
system clock.
Start
bit
D0 D1 D2
D3 D4 D5 D6
Stop bit
D7
Measure low period (9 bits) (data is H'00)
High period of
at least 1 bit
Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI
Rev. 3.00, 03/04, page 639 of 830