HD64F2168 Datasheet, PDF (483/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Initial
Bit Bit Name Value
2
BC2
All 0
1
BC1
0
BC0
R/W Description
R/W Bit Counter
These bits specify the number of bits to be transferred
next. Bit BC2 to BC0 settings should be made during an
interval between transfer frames. If bits BC2 to BC0 are
set to a value other than B'000, the setting should be
made while the SCL line is low.
The bit counter is initialized to B'000 when a start condition
is detected. The value returns to B'000 at the end of a data
transfer.
I²C Bus Format
Clocked Synchronous Serial Mode
B'000: 9 bits
B'000: 8 bits
B'001: 2 bits
B'001: 1 bits
B'010: 3 bits
B'010: 2 bits
B'011: 4 bits
B'011: 3 bits
B'100: 5 bits
B'100: 4 bits
B'101: 6 bits
B'101: 5 bits
B'110: 7 bits
B'110: 6 bits
B'111: 8 bits
B'111: 7 bits
15.3.5 I²C Bus Transfer Rate Select Register (IICX3)
IICX3 selects the IIC transfer rate clock and sets the transfer rate of IIC channels 3 to 5.
Initial
Bit Bit Name Value
7 to 4 

3
TCSS
0
2
IICX5
All 0
1
IICX4
0
IICX3
R/W Description
 Reserved
These bits cannot be modified.
R/W Transfer Rate Clock Source Select
This bit selects a clock rate to be applied to the I²C bus
transfer rate.
0: φ/2
1: φ/4
R/W IIC Transfer Rate Select
These bits are used to control IIC operation.
These bits select the transfer rate in master mode,
together with the CKS2 to CKS0 bits in ICMR. For the
transfer rate, see table 15.3. IICX5, IICX4, and IICX3
control IIC_5, IIC_4, and IIC_3, respectively
Rev. 3.00, 03/04, page 443 of 830