HD64F2168 Datasheet, PDF (764/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

22.2 PLL Multiplier Circuit
The PLL multiplier circuit generates a clock of 1 or 4 times the frequency of its input clock. The
PFSEL states and corresponding multiplier values are shown in table 22.5.
Table 22.3 PFSEL and Multipliers
Input Clock (MHz) PFSEL
Crystal Resonator 5 to 25
1
5 to 8.25
0
External Clock 5 to 33
1
5 to 8.25
0
Multiplier
1
4
1
4
System Clock
(MHz)
5 to 25
20 to 33
5 to 33
20 to 33
22.3 Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock (φ), and generates φ/2, φ/4, φ/8, φ/16,
and φ/32 clocks.
22.4 Bus Master Clock Select Circuit
The bus master clock select circuit selects a clock to supply the bus master with either the system
clock (φ) or medium-speed clock (φ/2, φ/4, φ/8, φ/16, or φ/32) by the SCK2 to SCK0 bits in
SBYCR.
22.5 Subclock Input Circuit
The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a
32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in
P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1.
When the subclock is not used, subclock input should not be enabled.
22.6 Subclock Waveform Forming Circuit
To remove noise from the subclock input at the EXCL pin, the subclock is sampled by a divided φ
clock. The sampling frequency is set by the NESEL bit in LPWRCR.
The subclock is not sampled in subactive mode, subsleep mode, or watch mode.
Rev. 3.00, 03/04, page 724 of 830