HD64F2168 Datasheet, PDF (20/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

16.3.8 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15).................................... 528
16.3.9 Status Registers 1 to 3 (STR1 to STR3) .............................................................. 529
16.3.10 SERIRQ Control Register 0 (SIRQCR0)............................................................. 536
16.3.11 SERIRQ Control Register 1 (SIRQCR1)............................................................. 539
16.3.12 SERIRQ Control Register 2 (SIRQCR2)............................................................. 544
16.3.13 Host Interface Select Register (HISEL)............................................................... 545
16.3.14 SMIC Flag Register (SMICFLG) ........................................................................ 546
16.3.15 SMIC Control Status Register (SMICCSR)......................................................... 548
16.3.16 SMIC Data Register (SMICDTR) ....................................................................... 548
16.3.17 SMIC Interrupt Register 0 (SMICIR0) ................................................................ 548
16.3.18 SMIC Interrupt Register 1 (SMICIR1) ................................................................ 551
16.3.19 BT Status Register 0 (BTSR0)............................................................................. 552
16.3.20 BT Status Register 1 (BTSR1)............................................................................. 554
16.3.21 BT Control Status Register 0 (BTCSR0)............................................................. 557
16.3.22 BT Control Status Register 1 (BTCSR1)............................................................. 558
16.3.23 BT Control Register (BTCR)............................................................................... 560
16.3.24 BT Data Buffer (BTDTR).................................................................................... 563
16.3.25 BT Interrupt Mask Register (BTIMSR)............................................................... 564
16.3.26 BT FIFO Valid Size Register 0 (BTFVSR0) ....................................................... 566
16.3.27 BT FIFO Valid Size Register 1 (BTFVSR1) ....................................................... 566
16.4 Operation .......................................................................................................................... 567
16.4.1 LPC Interface Activation ..................................................................................... 567
16.4.2 LPC I/O Cycles.................................................................................................... 567
16.4.3 SMIC Mode Transfer Flow.................................................................................. 569
16.4.4 BT Mode Transfer Flow ...................................................................................... 572
16.4.5 A20 Gate.............................................................................................................. 574
16.4.6 LPC Interface Shutdown Function (LPCPD)....................................................... 577
16.4.7 LPC Interface Serialized Interrupt Operation (SERIRQ) .................................... 581
16.4.8 LPC Interface Clock Start Request ...................................................................... 583
16.5 Interrupt Sources............................................................................................................... 584
16.5.1 IBFI1, IBFI2, IBFI3, ERRI.................................................................................. 584
16.5.2 SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, HIRQ12 .............................. 584
16.6 Usage Notes ...................................................................................................................... 587
16.6.1 Module Stop Setting ............................................................................................ 587
16.6.2 Usage Note of LPC Interface............................................................................... 587
Section 17 D/A Converter ................................................................................. 589
17.1 Features............................................................................................................................. 589
17.2 Input/Output Pins.............................................................................................................. 590
17.3 Register Descriptions........................................................................................................ 591
17.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 591
17.3.2 D/A Control Register (DACR) ............................................................................ 591
17.4 Operation .......................................................................................................................... 593
Rev. 3.00, 03/04, page xx of xl