HD64F2168 Datasheet, PDF (115/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 5.2 Correspondence between Interrupt Source and ICR
Register
Bit Bit Name ICRA
ICRB
ICRC
7
ICRn7
IRQ0
A/D converter
SCI_0
6
ICRn6
IRQ1
FRT
SCI_1
5
ICRn5
IRQ2, IRQ3
—
SCI_2
4
ICRn4
IRQ4, IRQ5
TMR_X
IIC_0
3
ICRn3
IRQ6, IRQ7
TMR_0
IIC_1
2
ICRn2
DTC
TMR_1
IIC_2, IIC_3
1
ICRn1
WDT_0
TMR_Y
LPC
0
ICRn0
WDT_1
IIC_4, IIC_5
—
[Legend]]
n:
A to D
: Reserved. The write value should always be 0.
ICRD
IRQ8 to IRQ11
IRQ12 to IRQ15
—
—
—
—
—
—
5.3.2 Address Break Control Register (ABRKCR)
ABRKCR controls the address breaks. When both the CMF flag and BIE flag are set to 1, an
address break is requested.
Bit Bit Name Initial Value
7
CMF
Undefined
6 to 1 —
All 0
0
BIE
0
R/W Description
R Condition Match Flag
Address break source flag. Indicates that an
address specified by BARA to BARC is prefetched.
[Clearing condition]
When an exception handling is executed for an
address break interrupt.
[Setting condition]
When an address specified by BARA to BARC is
prefetched while the BIE flag is set to 1.
R Reserved
These bits are always read as 0 and cannot be
modified.
R/W Break Interrupt Enable
Enables or disables address break.
0: Disabled
1: Enabled
Rev. 3.00, 03/04, page 75 of 830