HD64F2168 Datasheet, PDF (781/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

23.5 Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed
with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in
TCSR (WDT_1) cleared to 0.
In software standby mode, the CPU, on-chip peripheral modules, and clock pulse generator all
stop. However, the contents of the CPU registers, on-chip RAM data, I/O ports, and the states of
on-chip peripheral modules other than the PWM, PWMX, A/D converter, and part of the SCI are
retained as long as the prescribed voltage is supplied.
Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15, KIN0 to KIN15,
or WUE8 to WUE15), the RES pin input, or STBY pin input.
When an external interrupt request signal is input, system clock oscillation starts, and after the
elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and
interrupt exception handling is started. When exiting software standby mode with an IRQ0 to
IRQ15 interrupt, set the corresponding enable bit to 1. When exiting software standby mode with a
KIN0 to KIN15 or WUE8 to WUE15 interrupt, enable the input. In these cases, ensure that no
interrupt with a higher priority than interrupts IRQ0 to IRQ15 is generated. In the case of an IRQ0
to IRQ15 interrupt, software standby mode is not exited if the corresponding enable bit is cleared
to 0 or if the interrupt has been masked by the CPU. In the case of a KIN0 to KIN15 or WUE8 to
WUE15 interrupt, software standby mode is not exited if input is disabled or if the interrupt has
been masked by the CPU.
When the RES pin is driven low, system clock oscillation is started. At the same time as system
clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must
be held low until clock oscillation settles. When the RES pin goes high after clock oscillation
settles, the CPU begins reset exception handling.
When the STBY pin is driven low, software standby mode is cancelled and a transition is made to
hardware standby mode.
Figure 23.3 shows an example in which a transition is made to software standby mode at the
falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge of the NMI pin.
Rev. 3.00, 03/04, page 741 of 830