HD64F2168 Datasheet, PDF (216/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

7.9 Usage Notes
7.9.1 Module Stop Mode Setting
DTC operation can be enabled or disabled by the module stop control register (MSTPCR). In the
initial state, DTC operation is enabled. Access to DTC registers are disabled when module stop
mode is set. Note that when the DTC is being activated, module stop mode can not be specified.
For details, refer to section 23, Power-Down Modes.
7.9.2 On-Chip RAM
MRA, MRB, SAR, DAR, CRA, and CRB are all located in on-chip RAM. When the DTC is used,
the RAME bit in SYSCR should not be cleared to 0.
7.9.3 DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR, for reading and
writing. Multiple DTC activation sources can be set at one time (only at the initial setting) by
masking all interrupts and writing data after executing a dummy read on the relevant register.
7.9.4 Setting Required on Entering Subactive Mode or Watch Mode
Set the MSTP14 bit in MSTPCRH to 1 to make the DTC enter module stop mode, then confirm
that is set to 1 before making a transition to subactive mode or watch mode.
7.9.5 DTC Activation by Interrupt Sources of SCI, IIC, or A/D Converter
Interrupt sources of the SCI, IIC, or A/D converter which activate the DTC are cleared when DTC
reads from or writes to the respective registers, and they cannot be cleared by the DISEL bit in
MRB.
Rev. 3.00, 03/04, page 176 of 830