HD64F2168 Datasheet, PDF (847/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 25.11 I²C Bus Timing
Condition: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to 33 MHz
Item
Symbol Min.
Typ. Max. Unit Test Conditions
SCL input cycle time
t_SCL
SCL input high pulse width t
SCLH
SCL input low pulse width t
SCLL
SCL, SDA input rise time t
Sr
SCL, SDA input fall time t
Sf
SCL, SDA output fall time t_Of
SCL, SDA input spike
t_SP
pulse elimination time
12

3

5





20 + 0.1 C_b 



t_cyc


7.5*
300 ns
250
1
t_cyc
Figure 25.30
SDA input bus free time t_BUF
5
Start condition input hold t_STAH
3
time




Retransmission start
t
3
STAS
condition input setup time


Stop condition input setup t
3
STOS
time


Data input setup time
t_SDAS
0.5


Data input hold time
t_SDAH
0


ns
SCL, SDA capacitive load C_b


400 pF
Note:
*
17.5 t or 37.5 t can be set according to the clock selected for use by the IIC module.
cyc
cyc
Rev. 3.00, 03/04, page 807 of 830