HD64F2168 Datasheet, PDF (510/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Start condition generation
SCL
(master output)
SDA
(master output)
SDA
(slave output)
[5]
ICDRE
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W [7]
A
IRIC
IRTR
Interrupt
request
Interrupt
request
ICDRT
Address + R/W
ICDRS
Address + R/W
1
2
Bit 7 Bit 6
Data 1
Data 1
Data 1
Note: Do not set ICDR
during this period.
User processing
[4] BBSY set to 1 and
SCP cleared to 0
[6] ICDR write
(start condition issuance)
[6] IRIC clear
[9] ICDR write
[9] IRIC clear
Figure 15.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)
SCL
(master output)
8
9
SDA
Bit 0
(master output)
Data 1
[7]
SDA
A
(slave output)
ICDRE
IRIC
IRTR
ICDR
Data 1
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 2
[10]
A
Stop condition issuance
Data 2
User processing [9] ICDR write
[9] IRIC clear
[11] ACKB read
[12] BBSY set to 1 and
SCP cleared to 0
[12] IRIC clear ^{(Stop condition issuance)}
Figure 15.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode
(MLS = WAIT = 0)
Rev. 3.00, 03/04, page 470 of 830