HD64F2168 Datasheet, PDF (571/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

• STR2
R/W
Bit Bit Name Initial Value Slave Host Description
7 DBU27 All 0
6 DBU26
5 DBU25
4 DBU24
3 C/D2
0
R/W R
Defined by User
The user can use these bits as necessary.
R R Command/Data
When the host processor writes to an IDR2 register,
bit 2 of the I/O address is written into this bit to
indicate whether IDR2 contains data or a command.
0: Content of input data register (IDR2) is data
1: Content of input data register (IDR2) is a command
2 DBU22 0
R/W R Defined by User
The user can use this bit as necessary.
1 IBF2
0
R R Input Data Register Full
Indicates whether or not there is receive data in IDR2.
This bit is an internal interrupt source to the slave
processor (this LSI).
0: There is not receive data in IDR2
[Clearing condition]
When the slave processor reads IDR2
1: There is receive data in IDR2
[Setting condition]
When the host processor writes to IDR2 using I/O
write cycle
0 OBF2 0
R/(W) R
*
Output Data Register Full
Indicates whether or not there is transmit data in
ODR2.
0: There is not transmit data in ODR2
[Clearing condition]
When the host processor reads ODR2 using I/O read
cycle, or the slave processor writes 0 to the OBF2 bit
1: There is transmit data in ODR2
[Setting condition]
When the slave processor writes to ODR2
Note: * Only 0 can be written to clear the flag.
Rev. 3.00, 03/04, page 531 of 830