HD64F2168 Datasheet, PDF (149/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Initial
Bit Bit Name Value R/W Description
4 AST
1
R/W Basic Extended Area Access State Control
Selects the number of states for access to the basic extended
area. This bit also enables or disables wait-state insertion.
[ADMXE = 0] Normal extension
0: 2-state access space. Wait state insertion disabled
1: 3-state access space. Wait state insertion enabled
[ADMXE = 1] Address-data multiplex extension
0: 2-state data access space. Wait state insertion disabled
1: 3-state data access space. Wait state insertion enabled
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, this bit setting is ignored in 256-kbyte extended
area access and CP extended area access.
3 WMS1
0
2 WMS0
0
R/W Basic Extended Area Wait Mode Select 1 and 0
R/W _{Selects the wait mode for access to the basic extended area}
when the AST bit is set to 1.
00: Program wait mode
01: Wait disabled mode
10: Pin wait mode
11: Pin auto-wait mode
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, this bit setting is ignored in 256-kbyte extended
area access and CP extended area access.
1 WC1
1
R/W Basic Extended Area Wait Count 1 and 0
0 WC0
1
R/W _{Selects the number of program wait states to be inserted}
when the basic extended area is accessed when the AST bit
is set
to 1. The program wait state is only inserted into data cycles.
00: Program wait state is not inserted
01: 1 program wait state is inserted
10: 2 program wait states are inserted
11: 3 program wait states are inserted
When the CS256E bit in SYSCR and the CPCSE bit in BCR2
are set to 1, this bit setting is ignored in 256-kbyte extended
area access and CP extended area access.
Rev. 3.00, 03/04, page 109 of 830