HD64F2168 Datasheet, PDF (87/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

2.7.9 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode*, the upper eight bits of the effective address are ignored in order to generate a 16-bit
address.
Note * Not available in this LSI.
Table 2.13 Effective Address Calculation (1)
No Addressing Mode and Instruction Format
1 Register direct (Rn)
op rm rn
2 Register indirect (@ERn)
op
r
3 Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
op
r
disp
Effective Address Calculation
31
0
General register contents
31
0
General register contents
31
Sign extension
0
disp
Effective Address (EA)
Operand is general register contents.
31 24 23
0
Don't care
31 24 23
0
Don't care
4 Register indirect with post-increment or
pre-decrement
31
0
31 24 23
0
• Register indirect with post-increment @ERn+
General register contents
Don't care
op
r
1, 2, or 4
• Register indirect with pre-decrement @-ERn
31
0
General register contents
31 24 23
0
Don't care
op
r
1, 2, or 4
Operand Size
Byte
Word
Longword
Offset
1
2
4
Rev. 3.00, 03/04, page 47 of 830