HD64F2168 Datasheet, PDF (192/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

7.2.1 DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Initial
Bit
Bit Name Value
7
SM1
Undefined
6
SM0
5
DM1
Undefined
4
DM0
3
MD1
Undefined
2
MD0
1
DTS
Undefined
0
Sz
Undefined
[Legend]
*:
Don't care
R/W
—
—
—
—
—
Description
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0*: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0, by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0, by –2 when Sz = 1)
Destination Address Mode 1 and 0
These bits specify a DAR operation after a data
transfer.
0*: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0, by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0, by –2 when Sz = 1)
DTC Mode
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area in repeat
mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Rev. 3.00, 03/04, page 152 of 830