HD64F2168 Datasheet, PDF (341/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

11.7.3 Conflict between OCR Write and Compare-Match
If a compare-match occurs during the state after an OCRA or OCRB write cycle, the write takes
priority and the compare-match signal is disabled. Figure 11.19 shows the timing for this type of
conflict.
If automatic addition of OCRAR and OCRAF to OCRA is selected, and a compare-match occurs
in the cycle following the OCRA, OCRAR, and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is disabled. Consequently, the result of
the automatic addition is not written to OCRA. Figure 11.20 shows the timing for this type of
conflict.
Write cycle of OCR
T1
T2
φ
Address
Internal write
signal
FRC
OCR address
N
N+1
OCR
N
M
Compare-match
signal
Write data
Disabled
Figure 11.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used)
Rev. 3.00, 03/04, page 301 of 830