HD64F2168 Datasheet, PDF (27/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 171
Section 8 I/O Ports
Figure 8.1 Noise Canceler Circuit .............................................................................................. 208
Figure 8.2 Noise Canceler Operation.......................................................................................... 208
Section 9 8-Bit PWM Timer (PWM)
Figure 9.1 Block Diagram of PWM Timer ................................................................................. 251
Figure 9.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ..... 259
Figure 9.3 Example of PWM Setting.......................................................................................... 260
Figure 9.4 Example when PWM is Used as D/A Converter....................................................... 260
Section 10 14-Bit PWM Timer (PWMX)
Figure 10.1 PWMX (D/A) Block Diagram................................................................................. 261
Figure 10.2 PWMX (D/A) Operation ......................................................................................... 269
Figure 10.3 Output Waveform (OS = 0, DADR corresponds to T_L) .......................................... 272
Figure 10.4 Output Waveform (OS = 1, DADR corresponds to T_H) .......................................... 273
Figure 10.5 D/A Data Register Configuration when CFS = 1 .................................................... 273
Figure 10.6 Output Waveform when DADR = H'0207 (OS = 1) ............................................... 274
Section 11 16-Bit Free-Running Timer (FRT)
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer ....................................................... 278
Figure 11.2 Example of Pulse Output......................................................................................... 289
Figure 11.3 Increment Timing with Internal Clock Source ........................................................ 290
Figure 11.4 Increment Timing with External Clock Source ....................................................... 290
Figure 11.5 Timing of Output Compare A Output ..................................................................... 291
Figure 11.6 Clearing of FRC by Compare-Match A Signal ....................................................... 291
Figure 11.7 Input Capture Input Signal Timing (Usual Case) .................................................... 292
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD is Read)....................... 292
Figure 11.9 Buffered Input Capture Timing ............................................................................... 293
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1) ...................................................... 294
Figure 11.11 Timing of Input Capture Flag (ICFA to ICFD) Setting......................................... 294
Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................. 295
Figure 11.13 Timing of Overflow Flag (OVF) Setting............................................................... 295
Figure 11.14 OCRA Automatic Addition Timing ...................................................................... 296
Figure 11.15 Timing of Input Capture Mask Signal Setting....................................................... 296
Figure 11.16 Timing of Input Capture Mask Signal Clearing .................................................... 297
Figure 11.17 Conflict between FRC Write and Clear................................................................. 299
Figure 11.18 Conflict between FRC Write and Increment ......................................................... 300
Figure 11.19 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used)............................................... 301
Figure 11.20 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Used)...................................................... 302
Rev. 3.00, 03/04, page xxvii of xl