HD64F2168 Datasheet, PDF (307/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

10.3.4 Peripheral Clock Select Register (PCSR)
PCSR and the CKS bit of DACR select the operating speed.
Bit Bit Name Initial Value R/W Description
7 PWCKX1B 0
6 PWCKX1A 0
R/W PWMX_1 Clock Select
R/W _{These bits select a clock cycle with the CKS bit of}
DACR of PWMX_1 being 1.
See table 10.2.
5 PWCKX0B 0
4 PWCKX0A 0
R/W PWMX_0 Clock Select
R/W _{These bits select a clock cycle with the CKS bit of}
DACR of PWMX_0 being 1.
See table 10.2.
3 PWCKX1C 0
R/W PWMX_1 Clock Select
This bit selects a clock cycle with the CKS bit of DACR
of PWMX_1 being 1.
See table 10.2.
2 PWCKB 0
1 PWCKA 0
R/W PWM Clock Select B and A
R/W _{See section 9.3.5, Peripheral Clock Select Register}
(PCSR).
0 PWCKX0C 0
R/W PWMX_0 Clock Select
This bit selects a clock cycle with the CKS bit of DACR
of PWMX_0 being 1.
See table 10.2.
Table 10.2 Clock Select of PWMX_1 and PWMX_0
PWCKX0C
PWCKX1C
0
0
0
0
1
1
1
1
PWCKX0B
PWCKX1B
0
0
1
1
0
0
1
1
PWCKX0A
PWCKX1A
0
1
0
1
0
1
0
1
Resolution (T)
Operates on the system clock cycle (t_cyc) x 2
Operates on the system clock cycle (t ) x 64
cyc
Operates on the system clock cycle (t ) x 128
cyc
Operates on the system clock cycle (t ) x 256
cyc
Operates on the system clock cycle (t_cyc) x 1024
Operates on the system clock cycle (t_cyc) x 4096
Operates on the system clock cycle (t_cyc) x 16384
Setting prohibited
Rev. 3.00, 03/04, page 267 of 830