HD64F2168 Datasheet, PDF (460/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

14.9 Interrupt Sources
14.9.1 Interrupts in Normal Serial Communication Interface Mode
Table 14.13 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC to allow data transfer. The RDRF flag is automatically cleared to 0 at data
transfer by the DTC.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 14.14 SCI Interrupt Sources
Channel
0
1
2
Name
ERI0
RXI0
TXI0
TEI0
ERI1
RXI1
TXI1
TEI1
ERI2
RXI2
TXI2
TEI2
Interrupt Source
Receive error
Receive data full
Transmit data empty
Transmit end
Receive error
Receive data full
Transmit data empty
Transmit end
Receive error
Receive data full
Transmit data empty
Transmit end
Interrupt Flag
ORER, FER, PER
RDRF
TDRE
TEND
ORER, FER, PER
RDRF
TDRE
TEND
ORER, FER, PER
RDRF
TDRE
TEND
DTC Activation
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Priority
High
Low
Rev. 3.00, 03/04, page 420 of 830