HD64F2168 Datasheet, PDF (158/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

(2) In Address-Data Multiplex Extended Mode
(a) Bus Width: A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in
WSCR, and the ABWCP bit in BCR2.
(b) Number of Access States: Two or three states can be selected for data access via the AST and
AST256 bits in WSCR, and the ASTCP bit in BCR2. When the 2-state access space is designated,
wait-state insertion is disabled.
(c) Wait Mode and Number of Program Wait States:
i)
IOS Extended Area
When the IOS extended area is specified as a 3-state access space by the AST bit in WSCR, the
wait mode and the number of program wait states to be inserted automatically is selected by the
WMS1, WMS0, WC1, and WC0 bits in WSCR. Zero or one program wait state can be inserted
into address cycle. From zero to three program wait states can be selected for data cycle.
ii)
256-kbyte Extended Area
When the 256-kbyte extended area is specified as a 3-state access space by the AST256 bit in
WSCR, the wait mode and the number of program wait states to be inserted automatically is
selected by the WMS10, WC11, and WC10 bits in WSCR2. Zero or one program wait state can be
inserted into address cycle. From zero to three program wait states can be selected for data cycle.
iii) CP Extended Area
When the CP extended area is specified as a 3-state access space by the ASTCP bit in BCR2, the
wait mode and the number of program wait states to be inserted automatically is selected by the
WMS21, WMS20, WC22, WC21, and WC20 bits in WSCR2. Zero or one program wait state can
be inserted into address cycle. From zero to three program wait states can be selected for data
cycle.
The wait function for external extension is effective for connecting low-speed devices to the
external address space. However, this wait function may cause some problems when the operation
of bus masters other than the CPU, such as the DTC, are to be delayed.
Tables 6.7 to 6.14 show address-data multiplex address space and the bus specifications for the
basic bus interface of each area.
Rev. 3.00, 03/04, page 118 of 830