HD64F2168 Datasheet, PDF (556/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
5 IRQBSY 0
R
 SERIRQ Busy
Indicates that the LPC interface's SERIRQ signal is
engaged in transfer processing.
0: SERIRQ transfer frame wait state
[Clearing conditions]
• LPC hardware reset or LPC software reset
• LPC hardware shutdown or LPC software
shutdown
• End of SERIRQ transfer frame
1: SERIRQ transfer processing in progress
[Setting condition]
• Start of SERIRQ transfer frame
4 LRSTB 0
R/W  LPC Software Reset Bit
Resets the LPC interface. For the scope of
initialization by an LPC reset, see section 16.4.6,
LPC Interface Shutdown Function (LPCPD).
0: Normal state
[Clearing conditions]
• Writing 0
• LPC hardware reset
1: LPC software reset state
[Setting condition]
• Writing 1 after reading LRSTB = 0
Rev. 3.00, 03/04, page 516 of 830