HD64F2168 Datasheet, PDF (538/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 15.13 I²C Bus Timing (with Maximum Influence of t_Sr/t_Sf)
Time Indication (at Maximum Transfer Rate) [ns]
Item
t
cyc
Indi-
cation
t /t
Sr Sf
Influence
(Max.)
I²C Bus
Specifi-
cation
(Min.)
φ=
5 MHz
φ=
8 MHz
φ=
10
MHz
φ=
16
MHz
φ=
20
MHz
φ=
25
MHz
φ=
33
MHz
t
SCLHO
0.5 t
SCLO
(–t_Sr)
Standard
mode
–1000
High-speed –300
mode
4000
4000 4000 4000 4000 4000 4000 4000*¹
600
2500 1450 1100 950
950
950
950
t_SCLLO
0.5 t_SCLO
(–t_Sf )
Standard
mode
–250
High-speed –250
mode
4700
4750 4750 4750 4750 4750 4750 4750*¹
1300
2550 1500 1150*¹ 1000*¹ 1000*¹ 1000*¹ 1000*¹
t
BUFO
0.5 t
Standard
SCLO
–1000
4700
3800*¹ 3875*¹ 3900*¹ 3938*¹ 3950*¹ 3960*¹ 3970*¹
–1 t_cyc
mode
( –t )
Sr
High-speed –300
1300
2300 1325 1000*¹ 888*¹ 900*¹ 910*¹ 920*¹
mode
t
STAHO
0.5 t
SCLO
–1 t
cyc
(–t )
Sf
Standard
mode
–250
High-speed –250
mode
4000
4550 4625 4650 4688 4700 4710 4720*¹
600
2350 1375 1050 938
950
960
970
t
STASO
1t
SCLO
(–t_Sr )
Standard
mode
–1000
High-speed –300
mode
4700 9000 9000 9000 9000 9000 9000 9000
600
5300 3200 2500 2200 2200 2200 2200
t
STOSO
0.5 t
SCLO
+2t
cyc
(–t )
Sr
Standard
mode
–1000
High-speed –300
mode
4000
4400 4250 4200 4125 4100 4080 4061*¹
600
2900 1700 1300 1075 1050 1030 1011
t_SDASO
1 t *3
SCLLO
Standard
–1000
250
(master) –3 t
cyc
mode
(–t )
Sr
High-speed –300
100
mode
3150 3375 3450 3563 3600 3630 3659
1650 825
550
513
550
580
609
t
SDASO
1
t *3
SCLL
Standard
–1000
250
(slave)
–12
t *2
cyc
mode
(–t )
Sr
High-speed –300
100
mode
1300 2200 2500 2950 3100 3220 3336
–1400*¹ –500*¹ –200*¹ 250
400
520
636
Rev. 3.00, 03/04, page 498 of 830