HD64F2168 Datasheet, PDF(38/874 Page) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

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HD64F2168 Datasheet, PDF (38/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

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Section 14 Serial Communication Interface (SCI, IrDA, and CRC)

Table 14.1 Pin Configuration.................................................................................................. 355

Table 14.2 Relationships between N Setting in BRR and Bit Rate B..................................... 369

Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 370

Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 371

Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 372

Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 372

Table 14.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode)......................... 373

Table 14.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode) ........ 373

Table 14.8 BRR Settings for Various Bit Rates

(Smart Card Interface Mode, n = 0, s = 372) ........................................................ 374

Table 14.9 Maximum Bit Rate for Each Frequency

(Smart Card Interface Mode, S = 372).................................................................. 374

Table 14.10 Asynchronous Mode Clock Source Select............................................................ 378

Table 14.11 Serial Transfer Formats (Asynchronous Mode)................................................ 381

Table 14.12 SSR Status Flags and Receive Data Handling .................................................. 390

Table 14.13 IrCKS2 to IrCKS0 Bit Settings......................................................................... 419

Table 14.14 SCI Interrupt Sources........................................................................................ 420

Table 14.15 SCI Interrupt Sources........................................................................................ 421

Section 15 I2C Bus Interface (IIC)

Table 15.1 Pin Configuration.................................................................................................. 438

Table 15.2

Table 15.3

Table 15.3

Transfer Format .................................................................................................... 441

I2C bus Transfer Rate (1) ...................................................................................... 444

I2C bus Transfer Rate (2) ...................................................................................... 445

Table 15.4 Flags and Transfer States (Master Mode) ............................................................. 452

Table 15.5 Flags and Transfer States (Slave Mode) ............................................................... 453

Table 15.6 Output Data Hold Time ........................................................................................ 464

Table 15.7 ISCMBCR Setting ................................................................................................ 464

Table 15.8 I2C Bus Data Format Symbols.............................................................................. 466

Table 15.9 Examples of Operation Using the DTC ................................................................ 491

Table 15.10

Table 15.11

IIC Interrupt Source .......................................................................................... 494

I2C Bus Timing (SCL and SDA Outputs)......................................................... 495

Table 15.12

Table 15.13

Permissible SCL Rise Time (tsr) Values ........................................................... 496

I2C Bus Timing (with Maximum Influence of tSr/tSf)........................................ 498

Section 16 LPC Interface (LPC)

Table 16.1 Pin Configuration.................................................................................................. 509

Table 16.2 LADR1, LADR2 Initial Values ............................................................................ 526

Table 16.3 Host Register Selection......................................................................................... 526

Table 16.4 Slave Selection Internal Registers ........................................................................ 527

Table 16.5 I/O Read and Write Cycles ................................................................................... 568

Table 16.6 GA20 (PD3) Set/Clear Conditions........................................................................ 574

Rev. 3.00, 03/04, page xxxviii of xl

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