HD64F2168 Datasheet, PDF (85/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Table 2.12 Absolute Address Access Ranges
Absolute Address
Data address
8 bits (@aa:8)
16 bits (@aa:16)
Normal Mode*
H'FF00 to H'FFFF
H'0000 to H'FFFF
32 bits (@aa:32)
Program instruction 24 bits (@aa:24)
address
Note: * Not available in this LSI.
Advanced Mode
H'FFFF00 to H'FFFFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
H'000000 to H'FFFFFF
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32
The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in a instruction
code can be used directly as an operand.
The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their
instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the
instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data
in its instruction code, specifying a vector address.
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode can be used by the Bcc and BSR instructions. An 8-bit or 16-bit displacement
contained in the instruction code is sign-extended to 24-bit and added to the 24-bit address
indicated by the PC value to generate a 24-bit branch address. Only the lower 24-bit of this branch
address are valid; the upper eight bits are all assumed to be 0 (H′00). The PC value to which the
displacement is added is the address of the first byte of the next instruction, so the possible
branching range is –126 to +128-byte (–63 to +64 words) or –32766 to +32768-byte (–16383 to
+16384 words) from the branch instruction. The resulting value should be an even number.
Rev. 3.00, 03/04, page 45 of 830