HD64F2168 Datasheet, PDF (861/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Main Revisions and Additions in this Edition
Item
Page
Section 5 Interrupt
100
Controller
5.7.4 Note on IRQ Status
Registers (ISR16, ISR)
Section 12 8-bit Timer 305
12.1 Features
Section 12.3.4 Timer
312,
Control register (TCR) 313
Table 12.2 Clock Input to
TCNT and Count
Condition
Revisions (See Manual for Details)
Section 5.7.4 added.
• Cascading of TMR_0 and TMR_1
(Cascading of TMR_Y and TMR_X is not allowed)
 Operation as a 16-bit timer can be performed using
TMR_0 as the upper half and TMR_1 as the lower half
(16-bit count mode). TMR_1 can be used to count
TMR_0 compare-match occurrences (compare match
count mode)
Description amended.
TCR
Channel CKS2 CKS1 CKS0 Description
TMR_Y 0
0
0
Disables clock input
0
0
1
Increments at falling edge
of internal clock φ/4
0
1
0
Increments at falling edge
of internal clock φ/256
0
1
1
Increments at falling edge
of internal clock φ/2048
1
0
0
Setting prohibited
TMR_X 0
0
0
Disables clock input
0
0
1
Increments at falling edge
of internal clock φ
0
1
0
Increments at falling edge
of internal clock φ/2
0
1
1
Increments at falling edge
of internal clock φ/4
1
0
0
Setting prohibited
Note: * If the TMR_0 clock input is set as the TCNT_1
overflow signal and the TMR_1 clock input is set as
the TCNT_0 compare-match signal simultaneously,
a count-up clock cannot be generated. Setting of
these conditions should therefore be avoided.
Rev. 3.00, 03/04, page 821 of 830