HD64F2168 Datasheet, PDF (532/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

15.4.9 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15.28 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
SCL or
SDA input
signal
C
D
Q
Latch
C
D
Q
Latch
Match
detector
Internal
SCL or
SDA
signal
Sampling
clock
System clock
cycle
Figure 15.28 Block Diagram of Noise Canceler
15.4.10 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with clearing ICE bit.
Scope of Initialization: The initialization executed by this function covers the following items:
• ICDRE and ICDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, ICXR(other than ICDRE and
ICDRF))
• Internal latches used to retain register read information for setting/clearing flags in the ICMR,
ICCR, and ICSR registers
Rev. 3.00, 03/04, page 492 of 830