HD64F2168 Datasheet, PDF (686/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

 In the download processing, any interrupts are not accepted. However, interrupt requests
are held. Therefore, when the user procedure program is returned, the interrupts occur.
 When the level-detection interrupt requests are to be held, interrupts must be input until the
download is ended.
 When hardware standby mode is entered during download processing, the normal
download cannot be guaranteed in the on-chip RAM. Therefore, download must be
executed again.
 Since a stack area of 128 bytes at the maximum is used, the area must be allocated before
setting the SCO bit to 1.
 If a flash memory access by the DTC signal is requested during downloading, the operation
cannot be guaranteed. Therefore, an access request by the DTC signal must not be
generated.
4. FKEY is cleared to H'00 for protection.
5. The value of the DPFR parameter must be checked and the download result must be
confirmed.
 Check the value of the DPFR parameter (one byte of start address of the download
destination specified by FTDAR). If the value is H'00, download has been performed
normally. If the value is not H'00, the source that caused download to fail can be
investigated by the description below.
 If the value of the DPFR parameter is the same as before downloading (e.g. H'FF), the
address setting of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit (bit 7) in FTDAR.
 If the value of the DPFR parameter is different from before downloading, check the SS bit
(bit 2) and the FK bit (bit 1) in the DPFR parameter to ensure that the download program
selection and FKEY setting were normal, respectively.
6. The operating frequency are set to the FPEFEQ parameters for initialization.
 The current frequency of the CPU clock is set to the FPEFEQ parameter (general register
ER0).
The settable range of the FPEFEQ parameter is 5 to 33 MHz. When the frequency is set to
out of this range, an error is returned to the FPFR parameter of the initialization program
and initialization is not performed. For details on the frequency setting, see the description
in 20.3.2 (2) (a), Flash programming/erasing frequency parameter (FPEFEQ).
7. Initialization
When a programming program is downloaded, the initialization program is also downloaded to
the on-chip RAM. There is an entry point of the initialization program in the area from the start
address specified by FTDAR + 32 bytes of the on-chip RAM. The subroutine is called and
initialization is executed by using the following steps.
Rev. 3.00, 03/04, page 646 of 830