HD64F2168 Datasheet, PDF (548/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Figure 16.1 shows a block diagram of the LPC.
TWR0MW
BTDTR
FIFO _{TWR1 to 15}
(IN)
IDR3
IDR2
IDR1
Cycle detection
Module data bus
Parallel → serial conversion
SIRQCR0
SIRQCR1
SIRQCR2
Serial → parallel conversion
Address match
Control logic
HISEL
LAD0 to
LAD3
LADR12
LADR1
LADR2
LADR3
Serial ← parallel conversion
SYNC output
TWR0SW
BTDTR
FIFO _{TWR1 to 15}
(OUT)
ODR3
ODR2
ODR1
STR3
STR2
STR1
LSCIE
LSCIB
LSCI input
LSMIE
LSMIB
LSMI input
PMEE
PMEB
PME input
HICR0
HICR1
HICR2
HICR3
HICR4
PD0 I/O
PD1 I/O
PD2 I/O
Internal interrupt
control
IBFI1
IBFI2
IBFI3
ERRI
[Legend]
HICR0 to HICR4:
Host interface control register 0 to 4
LADR12H, 12L:
LPC channel 1, 2 address register 12H, 12L
LADR3H, 3L:
LPC channel 3 address register 3H, 3L
IDR1 to IDR3:
Input data register 1 to 3
ODR1 to ODR3:
Output data register 1 to 3
STR1 to STR3:
Status register 1 to 3
TWR0MW:
Bidirectional data register 0MW
TWR0SW:
Bidirectional data register 0SW
TWR1 to TWR15:
Bidirectional data registers 1 to 15
SIRQCR0 to SIRQCR2: SERIRQ control registers 0 to 2
HISEL:
Host interface select register
Figure 16.1 Block Diagram of LPC
SERIRQ
CLKRUN
LPCPD
LFRAME
LRESET
LCLK
LSCI
LSMI
PME
GA20
Rev. 3.00, 03/04, page 508 of 830