HD64F2168 Datasheet, PDF (479/874 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

15.3 Register Descriptions
The I²C bus interface has the following registers. Registers ICDR and SARX and registers ICMR
and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit
in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit
is set to 1, ICMR and ICDR can be accessed. The IIC registers are allocated to the same address.
Selecting register is carried out by means of the IICE bit in the serial timer control register
(STCR).
• I²C bus data register (ICDR)
• Slave address register (SAR)
• Second slave address register (SARX)
• I²C bus mode register (ICMR)
• I²C bus transfer rate select register (IICX3)
• I²C bus control register (ICCR)
• I²C bus status register (ICSR)
• I²C bus extended control register (ICXR)
• I²C SMbus control register (ICSMBCR)
15.3.1 I²C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the
three registers are performed automatically in accordance with changes in the bus state, and they
affect the status of internal flags such as ICDRE and ICDRF.
In master transmit mode with the I²C bus format, writing transmit data to ICDR should be
performed after start condition detection. When the start condition is detected, previous write data
is ignored. In slave transmit mode, writing should be performed after the slave addresses match
and the TRS bit is automatically changed to 1.
If IIC is in transmit mode (TRS=1) and the next data is in ICDRT (the ICDRE flag is 0), data is
transferred automatically from ICDRT to ICDRS, following transmission of one frame of data
using ICDRS. When the ICDRE flag is 1 and the next transmit data writing is waited, data is
transferred automatically from ICDRT to ICDRS by writing to ICDR. If IIC is in receive mode
(TRS=0), no data is transferred from ICDRT to ICDRS. Note that data should not be written to
ICDR in receive mode.
Reading receive data from ICDR is performed after data is transferred from ICDRS to ICDRR.
Rev. 3.00, 03/04, page 439 of 830